SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Petz who wrote (70390)8/31/1999 3:38:00 AM
From: Jeff R   of 1585803
 
It's my belief that any L2 cache integrated will always be full speed.

If the L2 cache is half speed then you'll require a lot more cache, up to double, to achieve similar performance. Every wonder why all the on-chip L2 caches produced thus far have been full speed.?

To achieve higher L2 cache speeds the circuit designer will partition the cache into a larger number of segmented blocks to achieve the faster access time.

I'm quite sure AMD is working on a socketed version of the Althon for budget minded applications similar to what Intel did with its Celron.
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext