Hi Scumbria; Re VHDL... I can tell you what your problem is right away! Your VHDL signal names are waaaaaaay too long, LOL!!! (Okay, I know that every engineer has his preferences.)
I prefer to add comments to the signal definitions, and use short names. If the code is really so long that the reader can't remember the signal names, then it needs to be broken up anyway.
Another thing I like to do is leaving in lower case all the VHDLL defined words, but leave the user stuff in capitals.
My biggest gripe about the language is the high level constructs it provides that don't synthesize to what you wanted. Because of this problem, I generally use low level constructs (i.e. logic, "with select", arithmetic), rather than high level constructs (convoluted if then else, process, etc). I only use process statements to infer flip flops. A lot of this attitude is from putting stuff into FPGAs where performance per gate is very important.
-- Karl
P.S. Example, counter by 3. I know it can be done in a lot less letters, but this is just an example of the style. Also, I just typed this in, I don't know if it even compiles correctly:
library IEEE; use IEEE.std_logic_1164.all;
entity CNT3S is port ( CLK: in STD_LOGIC; RESET: in STD_LOGIC; Q: out STD_LOGIC_VECTOR( 1 downto 0); ); end CNT3S;
architecture CNT3S_arch of CNT3S is
signal SELCNT: STD_LOGIC_VECTOR( 2 downto 0); -- Selector for CNT signal CNTQ,CNTD: STD_LOGIC_VECTOR( 1 downto 0); -- Counter bits
begin
SELCNT(2 downto 0) <= RESET & CNTQ(1 downto 0);
with SELCNT(2 downto 0) select CNTD(1 downto 0) <= "01" when "000", -- count "10" when "001", -- count "00" when "010", -- count "00" when others; -- clear
process (CLK) begin if CLK'event and CLK='1' then CNTQ <= CNTD(1 downto 0); end if; end process;
-- Output assignment. I like to explicitly include the array dimensions -- rather than just say Q <= CNTQ because it makes it more obvious later -- on just how much stuff I'm instantiating. I don't like terseness... Q <= CNTQ(1 downto 0);
end CNT3S_arch;
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