Hi Zeev Hed; Re the European filing, and first to file . We have access to this patent. The original Rambus patent includes the following restriction: "wherein the multiline bus has a total number of lines less than a total number of bits in any single address" (See #reply-15529407 for instance). This explicitly excludes earlier DRAM types, as well as SDRAM.
Here's the calculation for the 3 varieties of 64Mb SDRAM chips:
SDRAM 64Mb, x4 multiline bus line count:
CKE 1
CS# 1
WE# 1
CAS# 1
RAS# 1
DQM# 1
BAn 2
An 12
DQn 4
--
Total: 24
Row Address size: 12
Col Address size: 10
Bank Address size: 2
--
Total Address: 24
Note: 24 >= 24 so no infringement, even assuming that "single address" doesn't refer to the longest "single" address (i.e. the Row address, or perhaps the Row address + Bank address). The comparison with the preferred implementation from the Rambus patent is instructive:
(obsolete) RDRAM from patent
BUSDATAx 8
ADDRVALID 1
--
Total: 9
"Regular Access" address size: 40
Going back to the patent disclosure, it's useful to read the language having to do with how the bus is multiplexed, and how this is distinguished from the prior art:
Background of the Invention
...
Referring to FIG. 1, all modern DRAM, SRAM and ROM designs have interanl architectures with row (word) lines 5 and column (bit) lines 6 to allow the memory cells to tile a two dimensional area 1. One bit of data is stored at the intersection of each word and bit line. When a particular word line is enabled, all of the corresponding data lines are transferred onto the bit lines. Some prior art DRAMs take advantage of this organization to reduce the number of pins needed to transmit the address. The address of a given memory cell is split into two addresses, row and column, each of which can be multiplexed over a bus only half as wide as the memory cell address of the prior art would have required.
...
Comparison with Prior Art
...
Yet another object of this invention is to provide a method for transferring address, data and control information over a relatively narrow bus ...
...
Detailed Description
... The bus consists of a relatively small number of lines connected in parallel to each device on the bus. ... There is no need for separate address and data lines because address and data information can be sent over the same lines. Using the organization described herein, very large addresses (40 bits in the preferred implementation) and large data blocks (1024 bytes) can be sent over a small number of bus lines (8 plus one control line in the preferred implementation).
...
delphion.com
Since the prior art already included the concept of multiplexing row and column addresses onto the same pins, it is clear that Rambus excluded chips of that design by the language of their patent. The only possible explanation for the restriction of the bus to have "a total number of lines less than a total number of bits in any single address" is to distinguish from prior art DRAM. But if "single address" is intrerpreted as the total address (i.e. row + column + bank), the phrase would not exclude prior art DRAM. For example:
TMS44409 4Mbit x4 DRAM pin count:
/RAS 1
/CAS 1
/OE 1
/W 1
DQn 4
An 10
--
Total: 18
Row Address: 10
Col Address: 10
--
Total: 20
And since 18 < 20, this prior art DRAM would have been included under the Rambus claims. Data sheets for earlier versions of DRAM are hard to find, but the pin count to address comparison would be even worse, as they were typically built in x1 format. Here's the 4116 example, from back when DRAMs were 16Kbits in size (i.e. late 70s):
/RAS 1
/CAS 1
/WR 1
DIN 1
DOUT 1
An 7
--
Total: 12
Row Address: 7
Col Address: 7
--
Total: 14
bszx.iinf.polsl.gliwice.pl
Since 12 < 14, this prior art DRAM would have been included under the Rambus claims. Therefore, the only reasonable interpretation for "single address" is the row or column address. One could argue that the bank address should be included in the row or column address, but you are still left with about 2x as many bus pins as would be required in order to infringe on the Rambus patent.
-- Carl |
