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Politics : Formerly About Advanced Micro Devices
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To: Tenchusatsu who wrote (82711)12/13/1999 12:55:00 AM
From: Petz   of 1576161
 
Tench, re:<CuMine is half speed, quadruple width?>
Cancel my last post to Elmer -- if you are right, a lot of pieces fall together. The SRAM on a CuMine only has to operate at half speed, but the 256 bit width is four times wider than the path to the L2 cache in, say, an Athlon. Actually, this makes the cache access similar to RAMBUS access -- the cache latency might be slightly higher than an equally clocked Mendocino, if an entire cacheline isn't needed.

There's probably a memory benchmark or two for which the Coppermine is slower than an equally clocked Mendocino. Come to think of it, I do remember something like that from a review which may have been wrongly attributed to be a RAMBUS problem.

Petz
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