SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Intel Corporation (INTC)
INTC 50.80+0.5%12:28 PM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Maurice H. Norcott who wrote (9001)1/22/1997 2:58:00 PM
From: Paul Engel   of 186894
 
Maurice - Re:"Yield Drop"

This depends on how well debugged the new, smaller geometry process is before it is attempted to be ramped by production.

If the R & D group has done its job well, they will have proved not only proof of concept, but also demonstrated a minimum die yield before the production personnel agree to accept the process. Intel has strict guidelines for this process transfer.

Intel will have to have a bunch of new wafer steppers in place to print the layers that require the 0.25 micron minimum feature size. I'm sure Nikon has been real busy helping out in this department.

Bear in mind this simplistic argument. ASSUMING all layers scale by the ratio 0.25/0.35 (note - this implies a scaling ratio and DOES NOT IMPLY that ALL layers HAVE TO BE 0.25 micron minimum CD), the die size will be reduced by 1 -( 0.25/0.35)^2 = 1- 0.51 = 49%.

Also, IF INTEL adds a fifth layer of metal (the existing process uses four layers), extra compaction may be achieved to better the above number.

The 49% die size reduction implies that the number of possible die sites is nearly doubled = 2X.

Thus, if the percentage yield were to drop from from y (y = # good die/Total die sites/wafer on the 0.35 micron process) to y/2, the TOTAL number of good die would remain constant = (y/2)*2 = y! Maintaining an initial yield above this y/2 value produces gravy - and lots of it since speed increases will accompany the process geometry shrink.

Another factor - Intel's MMX processor was referred to as a pure CMOS device in some of the reports I read. This implies that Intel has already switched from BiCMOS to pure CMOS on the existing Pentium MMX process (presumably also 0.35 micron). Removing the EXTRA steps required to make bipolar drivers, guard rings for latch-up prevention and isolation, etc. will add further to the die reduction. Reducing the number of critical mask steps will also improve yields, or at least nullify the effects of the extra metal layer(s).

ALl in all, it could be a great bonanza for Intel - and shareholders as well!

Paul
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext