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Politics : Formerly About Advanced Micro Devices
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To: Dan3 who wrote (91690)2/5/2000 5:09:00 PM
From: Tenchusatsu  Read Replies (2) of 1576340
 
Dan, <And for the .18 process, Intel had to drop down to half speed cache. AMD has 128K of full speed L1 cache on Athlon .18, while Intel is limited to 32K full speed L1 cache at .18 - the cache story isn't quite so one sided as you are presenting it.>

Yet another myth perpetuated by the AMDroids. Yes, Coppermine's on-die cache only transfers data every other clock. (What more do you need when you transfer a full 256-bit cacheline in one gulp?) But the cache is STILL full-speed. It's not like the transistors run at half-speed or anything. That's ludicrous.

So why does Coppermine only transfer one cacheline every other clock? Maybe it has something to do with the P6 architecture itself, like the core itself can't consume a full cacheline every clock. After all, this IS a five-year-old architecture; I doubt even the original P6 architects were expecting a full-speed 256-bit BSB coming in the far future.

Tenchusatsu
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