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Politics : Formerly About Advanced Micro Devices
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To: Cirruslvr who wrote (91744)2/5/2000 9:34:00 PM
From: Tenchusatsu  Read Replies (2) of 1576628
 
Cirrus, <Actually, Saturn V posted here that the MPR said the cache is half-speed.>

I know MPR said that. I've seen the article. If I remember correctly (I don't have the article near me right now), they said it's technically a half-speed cache because a cacheline is transferred every other clock. They never said why, though. I contend it's a limitation in the P6 architecture. You AMDroids, however, assume the worst and think that Intel can't do full-speed on-die caches in 0.18u, which is absolutely false.

Tenchusatsu
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