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Politics : Formerly About Advanced Micro Devices
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To: Tenchusatsu who wrote (91785)2/6/2000 12:17:00 PM
From: Dan3  Read Replies (1) of 1577030
 
PB and Tenchusatsu, thanks for your responses.

I guess what's confusing me is the 4x 1/2 speed. 2x 1/2 speed or 4x 1/4 speed (or, like Rambus, 1/4x 8 speed - to fill the cache twice as fast) all seem to "fit". But 4x 1/2 speed seems twice as wide as is useful - it would be no faster than 2x 1/2 speed, so why take up the space?

Is there a latency associated with accessing even contiguous SRAM cache regions such that it is faster to switch address lines than address locations? (If I'm asking that question in a manner that makes any sense?)

Thanks for any response (if there is enough sense in the question to make it possible to answer!)

Dan
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