SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Scumbria who wrote (91828)2/6/2000 3:01:00 PM
From: Charles R   of 1577035
 
Scumbria,

<The complexity of trying to service multiple address streams on a single datapath is too high. It is much easier to provide a single datapath per stream, including a dedicated cache and bus.>

Though I have lost the touch to estimate the impact of the tradeoffs I can believe that. Especially in the context of MHz.

<Multiported caches tend to become very complex and slow. >

This is what the original topic was about - alternative to multiported cache is a cache running at a higher MHz sufficient to service requests from multiple execution units. Especially since we are talking about L2 caches, queueing theory might work in its favor. Now, there is a cache size/MHz issue and I don't intend to trivialize it.

Chuck
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  

HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2025 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News