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To: Phillip C. Lee who wrote (9576)3/17/1998 9:25:00 AM
From: Bill Jackson   of 213177
 
Phillip; Let us say we have a cache as big as main memory, then you will hit all the time, 100% hits, reducto ab... With zero cache you get zero hits, and the spectrum in between.
Since the G3 cache is larger it will have more hits(it will find the next instruction/datum in cache instead of elsewhere in MM).
A way to test to the extreme is to make every instruction/datum to not get hits in cache, but make the cache get dumped and filled as the cache controller tries to keep the next instruction/datum in there. With a look ahead you need to have evolving branches that make what looks like a hit turn into a miss as the final fetch occurs, theu the cache controller arrghs and goes to MM each time. This makes the chip work harder than turning off the cache completely.
In a perfect world with a brilliant look ahead you would need a tiny cache as the controller would win all the time. However in the fog of battle the look ahead can fail for various reason. Interruptions, dependencies etc.
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