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Politics : Formerly About Advanced Micro Devices
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To: Scumbria who wrote (98931)3/18/2000 3:00:00 PM
From: Daniel Schuh   of 1577086
 
That is interesting, Scumbria. This makes the architecture a little clearer, it's the SiS-style integration of north bridge+graphics chip. There is no reason in principle why this approach wouldn't work with the Athlon bus just as well as with the P6 bus. In practice, for this particular instance, it's probably unlikely, I assume Intel demanded a little something in return for getting raked over the coals on cost.

There does seem to be a granularity problem in getting a 128 bit bus off of 64mb worth of DDR SDRAM, though. 8 chips at 16bits in/out per chip is only 64 mbit/chip, which is maybe about standard density now, not 18 months from now. 4 chips at 32bits/chip is better, but 32 bits is a lot to drive off a conventional SDRAM chip, isn't it?

Cheers, Dan.
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