Sematech prepares economic model to gauge impact of accelerating chip technologies
A service of Semiconductor Business News, CMP Media Inc.
Story posted 9 a.m. EST/6 a.m., PST, 6/8/99
By J. Robert Lineback
AUSTIN, Tex. -- While technical committees debate a proposal to accelerate process shrinks in the industry's 1999 technology roadmap, Sematech here is completing work on an economic model that's aimed at helping chip makers decide when to use new manufacturing technologies.
The economic model is an attempt to fill a major void in the chip industry's ability to weigh the impact of technology acceleration and the use of new generations of fab gear on semiconductor profitability. After nearly a year of meetings, workshops, and trends analyses, Sematech is preparing to unveil the first version of its economic model to industry executives later this month at a board meeting of the consortium's international subsidiary in South Korea.
Sematech's efforts are being cheered by many semiconductor managers and analysts, who have often noted that the industry's roadmaps have only addressed technical issues in the deployment of next-generation processes.
"This is excellent," declares analyst Ronald Dornseif, who tracks semiconductor manufacturing technology at Dataquest in San Jose. "We need to be looking at the driving [market] forces, trends, and what that means in terms of technology needs. Then you can put the emphasis on a roadmap that makes technology and processes available to serve the market."
Once the economic model is ready, Sematech intends to make it available to semiconductor companies and capital equipment suppliers worldwide, according to Frank Robertson, chief operating officer of Sematech who has been overseeing the efforts. Sematech's model is not intended to give chip makers and their suppliers specific answers to business questions or technology strategies. Instead, Robertson said, the model is an attempt to provide a framework for "high-level discussions involving suppliers and integrated circuit manufacturers. It's not a magic formula that tells us how to proceed with development," he added.
The model will set up a wide-range of factors that affect industry economics and the profitability of next-generation technologies, according to industry managers involved in discussions with Sematech over the past year. These factors include the tradeoffs of two- and three-year technology cycles in the International Technology Roadmap for Semiconductors (ITRA), which is being updated this year by the Semiconductor Industry Association (SIA). Currently, a debate exist between aggressive logic manufacturers and mostly non-U.S. DRAM makers about a proposal to accelerate technology nodes in the 1999 update (see story from April issue of SBN).
In addition to addressing the speed of device shrinks, the economic model is intended to help semiconductor manufacturers decide when it makes economic sense to begin using larger 300-mm wafers in production, Robertson said. In fact, the entire effort to create a high-level model was started last summer when the 300-mm movement nearly broke down after chip makers delayed pilot lines using the larger diameter substrates and equipment suppliers began to openly complain about the lack of orders.
Eventually, the focus of meetings between Sematech, cautious chip makers and disgruntled equipment suppliers shifted from the troubled 300-mm movement to broader technology and business issues. "The major focus right now is on technology acceleration and the economic implications of the roadmap," Robertson explained.
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