SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Elmer who wrote (61093)6/9/1999 1:34:00 PM
From: Ali Chen  Read Replies (1) of 1572780
 
Elmer, <they don't know the performance boost Intel will enjoy with larger on-die L2 cache>
Intel will "enjoy" at most 3% "boost" as usual.
It is well known to everyone "skilled in the field"

The reason is in the Intergraph "Clipper" patents
on cache coherency support and bus snooping
protocols. Due to this and 4-way-associative cache
designs (I wonder where Intel stole those),
the cache system is already so effective that almost
no improvements could buy you any performance. This
is called "Amdahl law" if you are not familiar
with basic engineering.

You seem to never learn from your old and failed
expectations: remember FX-LX-BX performance "breakthroughs"?
Remember P-II-to-Xeon at the same clock rate?

<they are not comparing performance to Coppermine
and it's Camino chipset.>
Ha-ha-ha. See above.
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext