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>>Intel to Speed Its Plans To Use 12-Inch Wafers
By DEAN TAKAHASHI
Staff Reporter of THE WALL STREET JOURNAL
Intel Corp. said it will accelerate plans to adopt the next major generation of semiconductor-manufacturing technology, a move likely to spur a multibillion-dollar retooling of the industry.
The chip maker announced plans to begin manufacturing chips using silicon wafers that are 12 inches in diameter, and incorporate other technology advances for making cheaper, faster chips.
Intel's decision may cause rivals to accelerate their plans or risk falling behind, and trigger a long-awaited boom for makers of semiconductor equipment.
Company Profile: Intel
For consumers, the generational shift helps ensure that steady improvements in chip performance, known in the industry as Moore's Law, will continue.
"The industry has been waiting for somebody to step up," said Nathan Brookwood, an analyst at Insight 64 in Saratoga, Calif. Intel's move "will cause people to get off the dime."
Michael Splinter, an Intel vice president, said the company isn't sure exactly how much the moves will cost, "but you can say it will be in the billions."
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Intel's Inside Swells
Intel will move to larger silicon wafers in its chip plants to boost efficiency:
-Wafer diameter will increase to 12 inches from eight inches
-Provides double the surface area of current eight-inch wafer
-Allows for more than 2.4 times as many chips per wafer
-30% lower cost of producing chips
-$1.2 billion to be spent on Hillsboro, Ore., facility
Source: Intel
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Intel will start by spending $1.2 billion to upgrade a research factory in Hillsboro, Ore., with equipment that can handle 12-inch wafers. Today's silicon wafers, which are processed with chemicals and then sliced into individual semiconductor chips, typically are eight inches across. The change in size roughly doubles the surface area of each wafer, and allow 2.4 times the number of chips that can be produced at one time.
Intel, Santa Clara, Calif., which expects to spend $3 billion on capital expenditures this year, said the Oregon factory will begin deploying equipment in early 2000. Once the initial process is refined, Intel will roll out volume production beginning in 2002 at its other factories.
Gordon Moore, Intel's chairman emeritus, is credited with first observing that chip performance doubles roughly every 18 months. He has said the deployment of 12-inch wafers is likely to be the "largest industrial retooling in history." Sematech, an industry consortium, estimates that cost at anywhere from $14 billion to $30 billion.
Each 12-inch-chip factory is expected to cost $2.5 billion, up from about $1.5 billion today. The newer factories will generate more revenue, but the huge investment required could raise financial pressure on smaller competitors, analysts say. But those who stay in the business can't afford to be too far behind Intel, since the larger wafers could give an estimated 30% cost advantage over those produced using previous processes.
The transition was expected to start sooner. But a downturn in the chip industry from 1996 to 1998 left manufacturers with too much production capacity. In addition, Intel and International Business Machines Corp. had been shying away from taking a lead in the production shift because of past problems in trouble-shooting new processes. Except for a joint venture of Motorola Inc. and Siemens AG in Germany, most chip makers postponed their original plans to deploy 12-inch wafers in 1998.
Equipment makers felt even greater pain during the downturn. Besides lower sales of existing products, many had the further burden of spending on developing 12-inch equipment. Applied Materials Inc., the No. 1 equipment maker, has been ready to deploy a number of tools for the 12-inch wafer, but it lately had reduced its research investments because of lack of customer commitments. Only recently have a few large chip makers such as Taiwan Semiconductor Manufacturing Co. and South Korea's Samsung Electronics Co. began making commitments to the retooling.
Intel said it decided to step up its plans because of progress by the tool makers. "We were concerned the equipment wouldn't be ready, but now believe the tool set is available from multiple suppliers," Mr. Splinter said.
In addition to launching the new wafers, Intel said it will adopt a copper-based technology that IBM has pioneered in order to overcome resistance problems and create faster chips. It plans to incorporate the technology on a new manufacturing process that can make transistors just 0.13 micron across, compared with its current technology of 0.18 micron. Mr. Splinter said Intel will phase in the new technologies to reduce its risks.<<
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