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Politics : Formerly About Advanced Micro Devices
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To: Paul Engel who wrote (61264)6/10/1999 7:56:00 PM
From: Petz  Read Replies (1) of 1572808
 
Paul, you are 100% wrong on K7 voltages (the K7 uses a 2.5 volt Vcc which is reduced on-chip to 1.6 volts FOR THE PLL CLOCK ONLY)

The ISSC paper states:
The phase-locked loop (PLL) operates with a 2.5V supply, internally regulated down to 1.6V to satisfy oxide voltage stress limits. If oxide thickness is the reason for the lower supply voltage, I don't think it's likely that the oxide thickness is thicker on the rest of the chip.

Petz
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