SCUMbria - Did Dirk Meyer say the K7 was "soft error" free - or haven't they tested it yet ?
Paul
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Intel Scans For Soft Errors In Processor
By Anthony Cataldo, EE Times
Jun 16, 1999 (5:08 PM)
URL: techweb.com
Drawing attention to what it sees as a looming problem with submicron logic devices, Intel has developed a simulation tool to examine errors that occur in microprocessors as a result of intruding alpha particles, which can cause so-called "soft errors." Such errors will become a bigger problem in sub-0.25-micron process technologies, and the modeling and simulation process Intel has developed is the first step to alleviate it, the company said in a presentation this week at the Symposium on VLSI Technology, in Kyoto, Japan.
Intel has observed that one of the main sources of alpha particles inmicroprocessors come from the degradation of package materials surrounding the chip, and affects both the internal SRAM and logic nodes. The company, through tests conducted with Lawrence Livermore National Laboratory, has observed a marked increase in soft-error rate (SER) in circuits built in sub-0.25-micron CMOS technology, as supply voltages and capacitance falls and the size of an individual chip and its number of transistors continues to increase.
"We care about this because it can cause errors or even worse, it can disable your computer system," said Changhong Dai, project leader for Intel's Technology CAD Division, in Santa Clara, Calif. "Worst, are the silent errors that affect information in a computer system that go without being noticed."
Indeed, soft error rate is gaining more attention as an industrywide problem that is the inevitable consequence of scaling CMOS. In a paper to be presented Thursday at the VLSI Circuits Symposium, Bijan Davari of IBM Microelectronics' R&D division will list worsening soft-error rates as one of the main problems associated with lower supply voltages.
Dai said that there is no cause for alarm with current systems in use today, and added that Intel's tests were based on accelerated alpha particle emissions. Even so, Dai said that alpha particles pose a major reliability concern for Intel. The company is now manufacturing the majority of its microprocessors in 0.25-micron CMOS, and has started to make the transition to 0.18-micron this year.
"If you don't do something about it now, the problems can be immediate," Dai said.
The most pressing concern is alleviating soft-errors in larger systems, such as servers, that run on multiple processors and use large banks of DRAM, he said. Such a sentiment is in line with those voiced by IBM, which last year started offering DRAM memory modules with a error-correcting ASIC to protect DRAMs from cosmic particles, which can also cause soft errors.
To get a better handle on soft error occurrences, Intel took what it calls a comprehensive modeling and simulation approach. The first step was to determine the amount of charge required for a transistor to make a false switch when a particle penetrates beneath the drain of the transistor, which causes a soft error. The company took into account the many circuit types used in microprocessors, including domino logic, SRAM, register files, data-path latches and flip-flops.
Intel then developed an alpha strike model that takes into account the charge generation rate (based on the alpha particle energy loss rate in silicon); the loss of charge generation when it overlays the trench isolation boundary; and the charge collection efficiency.
The second major undertaking was coming up with a statistical algorithm to simulate a failure-in-time rate. To do this, Intel developed a "super-strike" concept that uses an algorithm based on six variables to determine the possible strike locations and failure ranges. For this to be effective, Dai said, the simulation must be repeated for every node on the chip.
Intel measured the SER on six-transistor SRAMs in 0.35-, 0.25-, and sub-0.25-micron generations. Though the models and simulation algorithms were developed for logic, SRAMs were used as a test vehicle because of their redundancy and predictability in verification. The company said the tools provide "excellent predictability," and will be an important part of its design planning.
While the tools provide Intel with an important first step, Dai did not disclose what specific measures Intel will take to make its microprocessors less susceptible to soft errors. He did say that none of the available choices will be easy to make.
Increasing the size of the nodes will increase the level of the charge needed to touch off a false switch, but the downside is that power consumption will go up. Using purified packaging materials with reduced alpha particle emissions has also been discussed, Dai said, but the cost is prohibitive. And in the near future, the company will have to come up with another strategy to prevent soft errors caused by cosmic rays bombarding a chip.
"There's no free lunch," he said. "Anything you suggest goes against the technology trend. If you want to implement a design fix, you are going to have to pay. But you first want to make sure you have an analysis tool before you try to fix the problem."
Others agreed that reliability concerns stemming from soft errors have taken on more importance at Intel. One source involved in circuit design at the company said that soft errors are the second biggest concern after leakage current in sub-micron designs.
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