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Politics : Formerly About Advanced Micro Devices

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To: Yousef who wrote (62113)	6/17/1999 1:33:00 PM
From: kash johal	Read Replies (2) of 1571408

Yousef, Re: "Please Krash ... Read my earlier post more closely. I make this exact statement that the higher I/O voltages need to be "tolerated" by the Source/Drain diodes. In both a .25um and .18um process, the S/D diodes have breakdowns well above 5V and Source-to-Drain breakdown doesn't occur until about 5V as well ... Thus with clever circuit design to control gate voltages, 3.3V I/O doesn't need dual gate oxides. This is especially true for the "slower" buses like PCI. In the future Krash, please read AND understand the material in my posts before "flaming", TIA. <ggg>" Yousef you are way out of your depth regarding circuit design. Suffice it to say all wafer foundries such as TSMC, UMC, CSM offer dual gate options on their deep sub-micron processess. For example they have several options for 0.18 micron with 1.8V core and ability to handle 3.3V I/O. The facts are that hundreds of designers and process folks have developed these processess for this very reason-resulting in extra masking steps and expense. Suffice it to say that it is NOT as simple as stacking transistors. Now tell us more why Intel has the worlds slowest 0.18 micron process you ignorant slut <GGG> Krash.

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