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To: Paul Engel who wrote (83700)6/18/1999 12:44:00 AM
From: Amy J  Read Replies (1) of 186894
 
RE: "all IIIs have ECC on the L2 caches - detect/correct 1 bit, detect 2 bit. Whatever microcode instructions they have are implemented in hard logic and/or "reprprogramable" flash. These are not subject to soft error upset."

Hi Paul, thanks for the information. I get this part.

RE: "actual ability of an alpha particle to cause such an upset is only recently a concern for random logic - as opposed to DRAM (and SRAM) where these concerns have been a reality for 23 years."

But I didn't understand this part. What is suspect to soft error upsets?

Thanks,
Amy J
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