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To: andy kelly who wrote (83795)6/18/1999 12:57:00 PM
From: Saturn V  Read Replies (1) of 186894
 
Ref- <Could you tell us what you conclude by reading between the lines of the Coppermine delay articles? >

This is my best effort at reading between the lines on the Coppermine problems. The chip layout design was completed late -(March April 99) time frame.This would put first Silicon in early May. It takes several weeks just to verify the design, and after the Silicon is completely clean, a large number of samples have to be accumulated and burnt in for any reliability problems. To meet the announced schedule, the first Silicon design had to be close to perfectly clean, with no unexpected reliability problems ,caused by the new design or process. Coppermine has an extra metal layer over the other the Dixon shrink , the 0.18 micron design which is being manufactured satisfactorily. So it is possible that a new problem was discovered on the extra metal layer.

It appears that the problem was discovered late, but is fixable by simple design change in the masks. [If process changes are required, the schedule impact would have been a lot worse.] If the design change is confined to the metal layer, the impact on the schedule is minimal.

The Celeron design was introduced flawlessly. The first Silicon was perfect and the part went immediately to manufacturing. Unfortunately this is not the norm. At least a few design tweaks are required for most designs before they are production worthy. Unfortunately the Celeron history of a flawless first design was not repeated.

All this is my best interpretation of what has been disclosed. I have fretted for the last six weeks over the status of Coppermine, and my worry was justified.
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