Process experts. Is it possible that Intel encountered "leakage and standby currents" problems in the 0.18u process, resulting in CuMine delay?
Kap.
From eetimes.com
At the current pace, CMOS transistors are set to top out at 1-V supply voltages. At that point, Davari said, the minimum effective (Leff) channel length of a transistor will shrink to 0.03 micron, which corresponds to a nominal channel length of 0.04 micron. At that point, leakage and standby currents will become unbearable.
As chip designers reduce Vdd, they must also drop the Vt of the transistors for faster switching speeds. But for every 100-millivolt reduction in the Vt, leakage and standby current jump by a factor of 10, Davari said.
If leakage and standby current get too high, they cause problems with burn-in, Iddq testing and functional dynamic circuits while raising the power dissipation at worst-case operating temperature, he said.
The problem is starting to crop up with 1.5-V devices. "As we get close to the 1-V [supply voltage] regime, the threshold voltage reductions are nowhere near the reduction of the supply voltage," said Davari. "Right now we've just reached the threshold of this deviation, and as we project into the future it gets more serious."
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