H & Q Part 2
June 17, 1999 - 9:04pm
Hambrecht & Quist
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Date: 6/18/99
2 of 4 DAC '99 Preview; Tackling Tough Problems in the Big Easy
Next week, EDA and SIP vendors will meet in New Orleans for the 36th Annual Design Automation Conference (DAC). DAC serves as the most significant conference for chip design tool providers, and typically announcements at DAC highlight the key issues facing the design community. We believe that the critical issues involve the next-generation of design tools for 0.18-micron designs, the recovery of the semiconductor industry and signs of life in Japan.
Problems in logic and physical verification have created the need for new tools, creating revenue opportunities for the majors and start-ups. The increasing complexity and smaller feature sizes of chips has created bottlenecks for both logic and physical verification. Verifying the logic in a million-gate chip has become a tricky problem using the traditional simulation methods that rely on driving test inputs (vectors) through a simulation model of the chip while measuring the outputs. The number of vectors increases exponentially with the number of gates making simulation more and more costly.
Automated test benches and simulation "cockpits" can be used to streamline the traditional simulation process considerably, and new formal methods are creating an alternative path towards logic verification. In addition, hardware-based emulation can accelerate the verification process and companies like Quickturn (now part of Cadence) and IKOS Systems appear to be doing well. We believe there are revenue opportunities for the leaders, particularly Synopsys
and Cadence, in the logic verification space, and also room for emerging players like Verisity, 0-In Design Automation, Sente and TransEDA.
The complexity of design also argues for moving to the next level of
abstraction, making the design process more efficient and streamlining
verification by minimizing coding errors. In the late 1980s, the use of high-level design languages (HDLs) and Synopsys' introduction of synthesis revolutionized the industry. In the same way, we believe that moving to higher-level languages, such as C, should reap major benefits in productivity. We see private companies, such as C-Level Design and CynApps (formerly C2 Design Automation) addressing this opportunity, as well as initiatives at the majors, primarily Synopsys.
Physical verification of deep submicron chips presents its own problems. Small feature sizes, multiple layers of metal, and fast speeds all conspire to make accurate physical extraction and verification a necessity prior to taping out a design. Mentor Graphics has been the biggest beneficiary in deep submicron
physical verification with their fast-growing Calibre tool driving their return to growth. On the private side, companies like Simplex and Frequency Technology are pursuing the fast growth opportunities in this sector.
Looking beyond 0.18 micron, we also see the industry facing sub-wavelength geometries where the feature sizes are smaller than the wavelength of light used in the lithography process. This will also stretch existing design, verification and manufacturing tools which must incorporate new technologies to account for the realities of the subwavelength era. Optical proximity correction and phase-shifted masks are two of the key technologies. Avant! and Mentor Graphics are both making pushes here, with private company, Numerical
Technologies taking an impressive leadership role.
Transition to time-based licensing can enhance overall visibility for
design tool companies. In general we believe that the trend towards time-based licenses (TBLs) should enhance the visibility of revenues in the industry, reducing the dependence on large perpetual licenses signed late in the quarter. Avant! and Synopsys appear to be the companies furthest along in this regard. Avant! has approximately 30% of its revenue coming from subscription-based licenses providing much better visibility on quarterly revenues than its peers. Synopsys has been moving towards greater than 50% of product revenue coming
from time-based licenses, preferring short-term one-year deals that do not build backlog per se, but create some "virtual backlog" given the 95%+ renewal rates. For this reason, we like both the Avant! and Synopsys approaches towards TBLs, and we favor smaller EDA companies pursuing these models, especially as they evolve into mature companies.
Japan is showing signs of life for some industry participants.
We believe that there is some hope that Japan will come to life with the 0.18- micron upgrade cycle. Some vendors in front-end logic tools, Quickturn and Synopsys, seem to be seeing a rosier picture in Japan. The back-end providers, Cadence and Avant!, have yet to see a pick-up, which could arguably be seen later on due to some lag in purchasing for back-end tools. Historically, Japan and the rest of Asia have been large growth contributors for all EDA sectors, especially in the mid-1990s. See Exhibit 2. Lately, Japan has been struggling, but a renewed purchasing cycle in Japan could contribute substantially to the outlook for all of the EDA players in the back half of 1999.
Exhibit 2. Asian and US / Europe Year-over-Year Growth
Source: H&Q
CHALLENGES:
Many of the existing design tools appear to be "broken," creating
opportunities for market share shifts among the majors and the entrance of nimble upstarts. As feature sizes shrink below 0.25 microns, many traditional EDA tools break down because they are built on the basis of approximations that do not hold true in very deep submicron (VDSM) geometries. For example, in the VDSM world,
interconnect delay rather than transistor delay begins to dominate timing considerations. Traditional synthesis tools focused on transistor delay and this helped allow the clear partitioning of synthesis and place-and-route. Today's 0.35- and 0.25- micron design flows have integrated various approximation techniques to help solve this problem with tools like floorplanning bringing some placement information into the front-end of the flow. At 0.18 microns, it is becoming clear that a whole new design creation flow is needed -- one that pulls synthesis and placement (and perhaps routing) together in an integrated design-creation tool. Clearly, we are describing a
new very high value software tool, and the winners should see good growth through the 0.18-micron upgrade cycle.
Both the core synthesis (Synopsys) and place-and-route (Cadence and Avant!) franchises are at risk during this transition. Among the majors, we believe that Synopsys has been the most aggressive early on in attacking this space, and may have a time-to-market advantage with their solution. Cadence is staging a credible effort, but only recently appears to have made it a strategic focus. Avant! has the best position in the 0.35/0.25- micron place- and-route based flow but lacks the proven synthesis technology to field a complete tool. Mentor will also be announcing an offering in this space, but
the core technology has not been tested in the marketplace. We also see a handful of new entrants making a strong entrance into this space, including Magma Design Automation, Monterey Design Automation, Sapphire Design Automation and Silicon Perspective. Others, including Aristo Technology, are offering complementary technologies that will help solve 0.18-micron design creation problem.
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