SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Intel Corporation (INTC)
INTC 34.50+2.6%Nov 21 9:30 AM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Johnnie W. who wrote (14965)3/20/1997 9:12:00 PM
From: Monica Detwiler   of 186894
 
Johhnie W - Six layers of transistors

Are you serious? Six layers of transistors , piled up on each other?

Just what do you know about semiconductor wafer fab processes?

Except for some exotic DRAM processes (trench capacitors, stacked-poly capacitors) all the transistors are on the same plane - perhaps the "planar process" may ring a bell.

The multitude of other layers are primarily interconnect layers for connecting the transistors (gates, source, drains) in the proper circuit configuration. I think this is what you are referring to as multiple layers.

These are not ACTIVE layers - they provide interconnect and isolation only.

Perhaps Maxwell can help set you straight. Check with him on the AMD thread.

monica

PS - multiple levels of transistors have been pursued in the past. Thin film MOS devices, fabricated in polysilicon, have been made but the transistor characteristics (leakage, threshold stability, etc.) are very poor and aren't suitable for production at this time.

m
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext