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Politics : Formerly About Advanced Micro Devices
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To: Richard Wang who wrote (65908)7/17/1999 6:52:00 PM
From: Elmer  Read Replies (2) of 1575941
 
Re: "Re: Another reason why you won't see fullspeed cache on the K7 anytime soon. ...Would you please explain this on not-so-technical terms."

Testing logic and testing memory take radically different approached. Memory is tester by algorithmically generating addresses and simple data in bit or byte form. Special circuitry (counters) can generate these addresses and move through an array reading and writing memory locations. Memory testers use an Algorithmic Pattern Generator to do this. This hardware can run at very high cycle rates.

Logic testing is a different animal. The stimulus must be stored in memory, read out and presented to the device at full speed. The expected response must be read from memory as well and compared to the output of the device. The memory would have to be many millions of cycles deep, cycle at ~1.25NS and it's far more expensive and problematic than a Pattern Generator. Try bringing all these signals together for 300+ channels just an inch or 2 away from the chip being tested! The problems go much deeper that I can go into here but in short, AMD would have to spend perhaps $100 million on new testers which are little more than lab characterization devices at this point. Furthermore the problems with 64 or 128 bits switching simultaniously on their BSB at 7-800MHz are enough for circuit designers to seek early retirement.

Intel on the other hand intends to drop the off die L2 and move it all on die. This eliminates the enormous investment in new equipment. They won't have to test any faster than the FSB which can be done with existing depreciated equipment. The secret is moving the cache on chip and the company with the lowest defect density can profitably make the largest die. Ever wonder why there are so few K6-3s around?

EP
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