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Politics : Formerly About Advanced Micro Devices
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To: grok who wrote (65978)7/18/1999 10:49:00 PM
From: Paul Engel  Read Replies (1) of 1573369
 
K7Nerd - Re: "The reason was the on-die 256kB L2 cache. Up to 500MHz there weren't too much problems, but above the fail-rate was
still to high to release the chip."

This implies that the L2 SRAM cache was a speed limiting factor.

Intel had already stated that 900 MHz SRAMs were already running on the 0.18 micron process - as part of the development cycle.

Paul
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