SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: fyo who wrote (66145)7/19/1999 9:03:00 PM
From: Tenchusatsu  Read Replies (1) of 1578294
 
<There have been some rumors that AMD would pull a 'DDR'-SRAM to make it more feasible to do 'full-speed' L2 cache. Any idea of how much the higher latency would hurt performance?>

Higher latency? I didn't know there will be any just by going to DDR SRAM. I thought that by moving to DDR SRAM, latency stays the same (in terms of absolute time), but burst transfer times are cut in half. This allows for a slight performance improvement for only a slight increase in cost. (Theoretically speaking, of course.)

This is different than Xeon's expensive CSRAM, where both latency and burst transfer times are shorter than Pentium III's BSRAM.

Tenchusatsu
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  

HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2025 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News