<Correct me if I am wrong but the 200MHz bus is between the Athlon and the chipset, not between the chipset and memory. In addition to talking to a memory subsystem a chipset is also talking to I/O, graphics subsystems, etc. Each of these interfaces can run at less than 200MHz and yet the system throughput overall will benefit. No?>
Think of the chipset as the crossroads between four interfaces: the processor bus, the memory, AGP, and PCI. Most communication is done between processor and memory. Then comes communication between AGP and memory, and finally PCI to memory. (Processor-to-AGP and processor-to-PCI traffic is relatively light.)
You can see that the main bottleneck becomes the memory channel. If there is only one PC100 SDRAM channel in the system, then the bandwidth between memory and chipset is 0.8 GB/sec. The bandwidth between processor and chipset is 1.6 GB/sec, which is overkill in regard to the memory bandwidth.
On the other hand, if DRDRAM were used, then the bandwidth between memory and chipset becomes 1.6 GB/sec, which then makes the extra bandwidth between processor and chipset much more useful.
Tenchusatsu |
