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To: Tenchusatsu who wrote (86239)7/27/1999 10:43:00 PM
From: kapkan4u  Read Replies (1) of 186894
 
<You can see that the main bottleneck becomes the memory channel. If there is only one PC100 SDRAM channel in the system, then the bandwidth between memory and chipset is 0.8 GB/sec. The bandwidth between processor and chipset is 1.6 GB/sec, which is overkill in regard to the memory bandwidth.

On the other hand, if DRDRAM were used, then the bandwidth between memory and chipset becomes 1.6 GB/sec, which then makes the extra bandwidth between processor and chipset much more useful.>

What is the combined bandwidth of PCI and AGP interfaces? If it is close to 0.8 GB/sec then there is no vacant bandwidth. Right? What about DDR266 SDRAM instead of DRDRAM?

Kap.

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