SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: grok who wrote (67263)8/1/1999 7:44:00 PM
From: Dan3  Read Replies (2) of 1574054
 
Re: People designing in drdram in a large server would use many multiple rambus channels.

Isn't the latency inherent in the rambus module due to the time it takes to set up, then read 8 cells, then set up and perform a serial transfer of that parallel data?

I'm not familiar with this chip set and haven't heard of a direct connection of rambus to any chip. Are you certain that there is no memory controller between the cpu and the memory busses? Are the bus controllers integrated into the chip? Is the chip running 400MHZ through its external bus?
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext