Packaging is becoming biggest cost in assembly, passing capital equipment
By James B. Brinton & By J. Robert Lineback
The growing cost of putting up a final chip-assembly plant seems like a drop in the bucket compared to the billions of dollars it now takes to build a wafer-processing fab. And even though projections show that back-end assembly plants are doubling in cost now for leading-edge chip packaging, there is more concern over the soaring costs of launching new packaging technologies, bills of materials, and final test. "You can get a pretty good [chip assembly] factory for $50 million, and the truth is that's chump change next to a wafer fab," says C. Scott Kulicke, CEO of Kulicke & Soffa Industries Inc. in Willow Grove, Pa. The head of the world's largest supplier of semiconductor assembly gear believes chip makers should be paying "much more attention" to the cost of testing and their loss of packaging expertise as assembly moves increasingly to contract manufacturers.
By moving more of their chip assembly to third-party manufacturers, IC companies are cutting back on their own engineering resources for packaging technologies, Kulicke maintains. "The industry is essentially being restructured into niches [equipment suppliers, plant-operating contractors, and chip companies], and that's dividing the infrastructure into 'silos,' he warns. "Along the way, the industry collectively has lost its knowledge base."
To get around that industry shift, K&S is trying to transform itself into a supplier of packaging materials, technologies, and "complete solutions" in addition to assembly equipment. The 49-year-old company already has spent more than $100 million on acquisitions, joint-ventures, and startups to expand its products and services into flip-chip technologies, multi-layer laminates, and advanced polymer materials. To make its new strategy work, K&S in July hired Alexander A. Oscilowski, chief operating officer of International Sematech, as vice president of strategic marketing charged with integrating services across product lines.
Kulicke says that his company is even kicking around the idea of getting involved in testing because chip packaging technologies increasingly are being held back by the way that ICs are handled and tested.
"The vast majority of flip-chip packages are on BGA [ball-grid array] substrates partly because of test requirements," he notes. "If you could adequately test the chips while they are still in the wafer format you wouldn't need these types of packages." Then, he says, smaller, cheaper chip-scale packages (CSPs) would be a viable option for more IC designs.
Reducing material costs is becoming a pressing issue in packaging plants as pinout counts and chip complexity increase. Most industry managers agree that the packages themselves and other materials such as leadframes are quickly becoming the biggest cost in assembly, surpassing capital equipment costs and plant depreciation. One reason for that is the current International Technology Roadmap for Semiconductors, which has set an aggressive pace for chip packaging and assembly. For example, the Semiconductor Industry Association's plan calls for a 46% drop in packaging costs--based on a price-per-pin--for "high-performance" devices. By 2011, the roadmap projects the packaging of a high-performance device to hit $2.43 per pin, down from $4.50 today.
That could end up becoming a real challenge because chip packaging is becoming both more critical and more difficult over the next decade. During that time, the roadmap expects the chip size for large microprocessors and system-level integrated circuits to shoot up 220%, from 340 to 750 square millimeters. The roadmap also predicts that the I/O bus width will rise 400% from 128 to 512 bits, and clock rates will move up 513% from 600 to 3,081 MHz.
The pressure here is coming from chip makers that are producing more and more ICs for highly cost-competitive consumer products. While these chips are being designed to sell at rock bottom prices, they also must deliver higher electrical performance and a greater amount of mixed-signal functions on a chip. As a result, chip makers are scrutinizing packaging and testing costs more than ever.
Fortunately, however, packaging costs on a per-pin basis have "come down a lot in the past two years," according to Robert Marr, president of Abpac Inc., a Phoenix IC assembler. He predicts that these costs will continue to fall. And in two years, he expects them to start falling more rapidly as technologies such as chip-scale packaging mature and packaging can take advantage of less costly materials and production techniques. Also helping to lower costs will be the emergence of more efficient production facilities, he adds.
But it probably won't be all that easy. Packaging costs vary wildly and it remains an open question whether the industry can keep up with the demands of the SIA roadmap. Packaging cost is generally a matter of package size and IO, notes Robert Crowley, president of Redpoint Research Inc., in Portland, Ore.
"With QFPs and SOP packages, cost is almost directly proportional to IO; with BGA and CSP, it's more a matter of package area," he says, adding that both area and IO are going up fast.
There may be new ways to attack the problem, however. One approach would be to make more efficient use of such existing packaging technologies as BGA. Motorola Inc.'s Semiconductor Products Sector has begun to put multiple unconnected chips in a single package. "This is not an MCM [multichip module]," says Crowley. "Instead, it is a way of cutting area and making more efficient use of the substrate." Using both can save money.
Motorola also is reducing costs by going to techniques like mold-array processing to make packaging more of a batch process. In mold-array processing--the "Hershey Bar" approach--an array of 5-to-20 devices is laid down in a strip, and the packaging cast around it using a single cavity. After casting, the packages are sawed up. "This makes the most effective use of the substrate," comments Crowley, and offers throughput savings since multiple packages are made simultaneously.
What may yet offer the most cost reduction potential is CSP, the minimalist's package, but it still hasn't fulfilled its glowing predictions due to the delay of Direct Rambus memory production.
A forecast last year by Tessera Inc., the microBGA developer, predicted that CSP costs would drop to one penny per IO by mid-1999. But such analysts as Steve Berry, president of Electronic Trend Publications in San Jose, maintain that the cost is still closer to two cents per /IO today. The San Jose analyst expects the cost to hit 1.5 cents per IO sometime in 2000, the exact time depending on how fast Rambus ramps up and whether CSP starts being used in other DRAM families such as DDR.
The way it looks now to such analysts as Brian Mattis of IC Insights, Inc. in Scottsdale, Ariz., CSP will add as much as 10% to the cost of early Rambus chips. Once volume rises, Redpoint's Crowley believes efforts will shift to the use of more economical CSP package materials. But that is still a year or more away.
But CSP is worth its higher price for some applications. Chip makers such as Intel already are shipping millions of flash-memory chips monthly in CSP packages. Reliability of these CSP packaged devices equals or exceeds that of units in standard packaging, according to Gary Fleeman, U.S. memory product manager for Advantest Corp., based in Austin, Tex.
Because of this, when volume CSP does arrive, analysts and assemblers expect the package price will drop quickly in price. This will be especially true, they say, for large-area, low-pin-count, low-power-dissipation devices like DRAM.
While the costs of equipping new assembly plants may be rising too, factory managers are confident they can drive down their manufacturing costs with the new equipment and factory automation. The cost of that equipment, software, and other systems will probably push the average cost of a chip assembly plant to $40 million over the next several years, as compared to about $20 million for starting up a packaging plant today, according to analysts.
But some experts don't believe the price of an assembly plant will go that high. In any event, such an advanced packaging facility will offer far more flexibility and productivity than today's plants, figures Abpac's Marr. His company, which specializes in fast-turnaround BGA and chip-scale packages, has just put the finishing touches on a new automated test and assembly floor in Phoenix. It is a robotic, cell-and-site design, which can run with a bare minimum of human operators. It is aimed specifically at what Marr calls "mass customization"--the ability to move a quickly changing mix of products rapidly through test and assembly.
The new production line is built around ESEC SA's AutoLine technology and Fastech's FactoryWorks shop-floor automation system from its Brooks Automation Inc. subsidiary. Marr claims that the line can be completely reprogrammed in minutes from a single server computer. After fixtures are swapped, the line is ready to go again.
Factories such as this can reach utilization rates of 80% or more on even mixed short runs, Marr estimates. As a result, he expects up to fivefold productivity improvements. All of Abpac's software is Oracle based, allowing a seamless merger with the rest of the company's tracking and management systems, he says. This should boost productivity and cut costs even more, he adds.
Similar developments are under way at other suppliers. PRI Automation Inc. in Billerica, Mass., and partners such as K&S have one now under construction in the Philippines for Amkor/Anam Pilipinas Inc. The new facility is expected to place more equipment on its production floor for plastic BGA assembly by using material-transporting automation and work-tracking software.
Automating these advanced packaging plants, should make it possible to move final assembly operations back to the U.S. and Europe from the low-labor cost regions of Asia, predicts Ron France, PRI's manager of industry solutions. Experts agree that chip makers are now seriously considering plans that would call for moving backend and frontend chip manufacturing operations more closely together in order to reduce cycle times.
Motorola, for example, is starting to locate frontend and backend operations on a single site by locating bump-assembly-test (BAT) packaging lines next to its wafer fabs. "As assembly and test move into newer packaging technologies, like flip-chip, we are [making this move]," says Bill Walker, Motorola's senior vice president running manufacturing operations. "We have [located] BAT1 in Austin and we will be doing [the same thing] in our next major facility." For example, he says, Motorola is "looking at doing this in China to reduce cycle times."
The movement of assembly operations next to wafer fabs has long made sense to Scott Kulicke. "This is one of my 'hobby horses,' he says. "Most merchant semiconductor companies won't admit it but there is always a couple percent yield loss that's unaccounted for in the shipment of wafers from fabs to assembly shops. It seems to evaporate somewhere over the Pacific Ocean," he notes, "and no one is [held] accountable for the loss.
"I have always argued that ultimately assembly should be more tightly coupled to the fab [in a single location]," Kulicke adds, "with one manager--the fab manager--responsible for yield."
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