And here I go again:
<In the last 6 months, VC DRAM and DDR DRAM have begun entering production, with a cost increase much smaller than rambus, and performance improvements of up to 260% (for DDR 266 burst and streaming) latency improvement is similar to rambus.>
First of all, where do you get that 260% number from? Your math isn't consistent: you say there's only a 33% improvement (in bandwidth and streaming) from Rambus 300/600 to 400/800. But then you say there's a 260% increase from PC100 SDRAM to PC266 DDR SDRAM. In case you haven't noticed, 266 is 166% more than 100, not 260%.
And that's not your only double-standard. When it comes to Rambus 400/800, you agree that the doubling in bandwidth over PC100 SDRAM doesn't contribute to a doubling of actual memory performance. Yet when it comes to DDR SDRAM, you completely ignore the standard you apply to Rambus when you say that it will exhibit a 166% (correcting your math) performance improvement.
Please, Dan, I'd like to give you the benefit of the doubt, but with this flawed logic, I'm about to associate you with the rest of the anti-Rambus FUD-sters.
<VC100, VC133, DDR 200 and DDR 266 standards offer substantial performance increases over PC100 at little additional cost.>
First of all, where's the support for VC100 and VC133? All we have are a few foils; no commitment from the DRAM manufacturers, and certainly no endorsement from the "Anything But Rambus" crowd like those backing DDR.
And second, the phrase "little additional cost" is misleading. You might want to consider the additional cost of 180 to 200 pins on the memory controller. Or the fact that Sony commented that DDR SDRAM has stability problems. Or the fact that DDR SDRAM isn't very efficient in using its theoretical bandwidth. (With DDR, the burst times shorten because of the double-pumped data, but turn-around times still don't change, and multi-source traffic will make DDR choke with sluggishness compared to Rambus. Just ask Dell, who said that DDR only achieves 60% utilization of bandwidth, compared to 95% for DRDRAM.)
<Additional pins don't cost that much.>
Then tell me why Intel is trending towards lower pins. If you didn't know already, the 810 Whitney chipset features a new "Accelerated Hub Architecture" where 8 pins provides double the bandwidth of a PCI bus. The 810 chipset also features an LPC interface for its firmware hub. LPC stands for "Low Pin-Count." The chipset also features an AC97 slot for Audio/Modem cards. Have you noticed how narrow that slot is? Check out this page for details:
anandtech.com
By the way, low pin-count is not just a Whitney low-end thing either. The desktop Camino chipset and the server/workstation Carmel chipset will also feature the "Accelerated Hub Architecture" and the LPC interface.
<By the way, DDR 400 standards are being developed to yield the same per pin transfer rates as rambus>
Wrong. DDR 400 yields 400 Mbit/sec on each pin. Rambus 400/800 yields 800 Mbit/sec on each pin. DDR 400 will still require double the pin-count of DRDRAM in order to match the bandwidth. Then we go back to the inefficiencies of DDR in the first place, yada yada.
<Rambus's business plan assumed that its competition would never improve - a very bad assumption to make in the high tech electronics industry.>
And what makes you so sure that Rambus is going to sit on its own tooche and not develop anything after DRDRAM 400/800?
Dan, your whole post proves to me that you are not merely "skeptical" of Rambus. Instead, you're more interested in spreading inaccuracies in a vain attempt to justify your anti-Rambus stance. If you're going to do that, at least try and make sure that what you say is accurate before you cut loose with the arguments.
Tenchusatsu |
