OT
Scumbria,
Is this an alternative design to RDRAM? TIA
IBM plans 500-MHz bus for Power4 processor
By Will Wade
EE Times
(08/18/99, 6:14 p.m. EDT)
PALO ALTO, Calif. — IBM Corp. expects its next-generation Power4 microprocessor to communicate with other chips in a system using a 500-MHz bus. Detailing the design at the annual Hot Chips technical conference this week, IBM said the bus' increased bandwidth will be essential to delivering higher performance in upcoming servers and workstations.
"How the microprocessor communicates with the chip set is critical," said Frank Ferraiolo, a senior engineer on the design team of the Power4 processor. "With current technology the bandwidth is limited, so the processor is data-starved."
Even as MPUs pass the 600-MHz barrier and continue to process more data internally, Ferraiolo noted, power is not used effectively because it can't be pushed off the processor at the same speeds. Bus speeds of 100 MHz, beginning to migrate to 133 MHz, dominate current designs.
IBM uses a technology known as a synchronous wave-pipelined interface, or an elastic interface, for the Power4 I/O. The key is controlling latency. Not only does the design minimize latency as data moves on and off the chip, it also has a FIFO on the receive side so the processor can synchronize data transfers.
<SNIP>.......... |
