Let me ask a question of the technicians on this thread. Isn't pin count the ultimate determining factor in the years ahead. Sorry to sound simplistic, but everything I have read seems to indicate that pin count eventually presents roadblocks to both maximizing the capabilities of SDRAM and integrating memory effectively on a microprocessor. If pin count is, in fact, the ultimate determinate, why isn't Rambus the clear universal winner, because on pin count they always, always win.
Am I wrong or just dumb? or both.
pomp,
i am certainly no techie but let me show you what dell says on that issue...
"Rambus offers a major advantage for future bandwidth expansion. Adding bandwidth with Rambus consists of adding another channel with 33 signal pins.
In comparison, an additional SDRAM interface requires 132 pins. Although an additional 132-pin interface may be a reasonable approach for expanding server memory, it is not appropriate for workstations or desktop PCs due to the component cost and system board space required. Moreover, increasing the clock rate or widening the data path beyond PC 133 parameters for a single SDRAM channel will increase the difficulty of controlling emissions, maintaining signal integrity, and meeting timing margins."
did someone ask for a killer app?
"Interference, discussed earlier, is an important factor in memory performance. Interference caused by simultaneous memory activity from multiple sources such as video, network, hard-disk drives, and processors is common today. As Windows 2000 replaces older operating systems, its improved management, security, backup, and virus scan capabilities will greatly increase simultaneous memory activity and the inherent interference caused by this activity. Rambus' ability to support simultaneous activity through its page management and pipelining schemes (reads and writes can be interleaved) will offer a significant performance advantage"
"Processor bus speed increases are not the only techniques for improving the path to a Rambus memory interface. Rambus' reduced pin count makes it feasible to integrate the memory interface directly onto a microprocessor chip.In this case, the logic normally associated with the processor-bus-to-memory-bus interface would run at full processor clock speeds, significantly reducing latency."
i'll let someone else answer your last question!
unclewest
:o)
some of us do think rmbs is clearly the winner.
thanks doug! |
