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Cadence's chip packaging design system analyzes I/O, board layouts
A service of Semiconductor Business News, CMP Media Inc.
Story posted 10:15 a.m. EST/7:15 a.m., PST, 8/23/99
MESA, Ariz.--During this week's High Density Interconnect (HDI) conference here, Cadence Design Systems Inc. plans to roll out a new development package that merges electrical and physical design capabilities into a single environment, called the SpecctraQuest.
According to Cadence, the SpecctraQuest environment features a unique design flow and methodology that enables engineers to explore packaging options, specifications and the implementation of finished products. The environment marries the SpecctraQuest simulation technology with a 3-D parasitic extraction engine from Ansoft Corp., a design automation partner of Cadence.
"While most environments provide only for post-layout extraction with little correlation to the actual physical layout, the Cadence/Ansoft flow lets designers make a number of important determinations that can impact both chip I/O design and board design," said Nicholas Csendes, chief executive officer of Ansoft, based in Pittsburgh, Pa.
The new environment leverages analysis of both the chip I/O and printed-circuit board design, "allowing changes to be made to parameters that affect the entire chip-package-board flow," said Dave DeMaria, vice president of marketing for PCB and packaging products at San Jose-based Cadence. "This is a tremendous benefit to our customers, who are having to take a more holistic approach to their designs," he added
The SpecctraQuest for IC packaging will be available later in the third quarter on both Windows NT and Unix-based platforms as part of Cadence's Advanced Packaging Ensemble tool suite. The design suite has a list U.S. priced of $110,000.
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