Pravin, re:<I really don't think you can make problem traces skinnier. They are already at minimum width, or if they are not, are at a width needed for whatever they are driving. If the traces are on different layers, you can translate one of them so they are not on top of each other. If they are on the same layer, you can increase the spacing between them. If they are on they same layer and you have copper, you can decrease their thickness (not width).>
So, do you think the CuMine delay is consistent with the turnaround time for a re-layout? I thought Paul indicated that at least part of the correction was process-related rather than mask related.
BTW, you were right on the capacitance issue except for inbetween layers.
Isn't crosstalk not just a capacitance issue, but also inductive pickup? Seems like shorter traces radiate less energy and capture less energy, but closer distances increases the energy transfer, and lower voltage circuits have less margin. So, net-net, does inductive and capacitive crosstalk get worse for smaller geometry?
Sorry to ask so many questions, but you seem to know more about this issue than I do.
Petz |
