NHBob
Pulled this off Patent web site from Aug 17
164.195.100.11
United States Patent 5,939,913
Tomita August 17, 1999
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DLL circuit and semiconductor memory device using same
Abstract
The present invention supplies a first delay control signal generated by a DLL circuit to a first variable delay circuit which generates a control clock by delaying a clock for a prescribed time period. The DLL circuit comprises: a first delay loop, comprising a second variable delay circuit and a third variable delay circuit connected in series, to which the clock is supplied; a phase comparator which is supplied with a clock which delays an integral factor of 360.degree. of said clock from the clock, as a reference clock, and the output of the first delay loop, as a variable clock; and a delay control circuit which generates said first delay control signal in accordance with a phase comparison result signal from the phase comparator such that there is no phase difference with said two supplied clocks. The second variable delay circuit is supplied with the first delay control signal. The third variable delay circuit has a delay time of .beta..degree. in accordance with a second delay control signal generated by a .beta..degree. detecting circuit. As a result, the second variable delay circuit generates a delay time of approximately 360.degree.-.beta..degree.=.alpha..degree.. By similarly controlling the delay time of the first variable delay circuit by means of this first delay control signal, the control clock output therefrom is phase delayed by .alpha..degree. from the clock.
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Inventors: Tomita; Hiroyoshi (Kawasaki, JP)
Assignee: Fujitsu Limited (Kanagawa, JP)
Appl. No.: 019197
Filed: February 5, 1998
U.S. Class: 327/158; 327/159; 327/236; 331/DIG.2; 375/376
Intern'l Class: H03L 007/06
Field of Search: 327/158,159,161,233,236,261,156 331/DIG. 2 375/376
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References Cited [Referenced By]
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U.S. Patent Documents
5642082 Jun., 1997 Jefferson 327/159.
5712884 Jan., 1998 Jeong 327/158.
5815016 Sep., 1998 Erickson 327/158.
Primary Examiner: Cunningham; Terry D.
Assistant Examiner: Kim; Jung Ho
Attorney, Agent or Firm: Nikaido Marmelstein Murray & Oram LLP
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Claims
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1. A DLL circuit which generates a control clock delayed by a prescribed phase .alpha..degree. from a first clock, said DLL circuit comprising:
a first variable delay circuit, which inputs said first clock and generates said control clock;
a first delay loop, which inputs said first clock and comprises a second variable delay circuit and a third variable delay circuit connected in series;
a first phase comparator, which compares a phase of a reference clock having a phase delay equal to an integral factor of 360.degree. from said first clock with a phase of a first variable clock output from said first delay loop, and generates a first phase comparison result signal corresponding to this phase difference;
a first delay control circuit, which receives said first phase comparison result signal and supplies a first delay control signal causing the phases of said reference clock and said first variable clock to coincide, to said second variable delay circuit and said first variable delay circuit; and
a .beta..degree. detecting circuit which generates a second delay control signal providing said third variable delay circuit with a delay time of .beta..degree. (=360.degree.-.alpha..degree.) of said first clock.
2. The DLL circuit, according to claim 1, wherein said .beta..degree. detecting circuit comprises
a second delay loop, which inputs said first clock and comprises a plurality of variable delay circuits connected in series;
a second phase comparator, which compares the phase of said reference clock with the phase of a second variable clock output from said second variable loop, and generates a second phase comparison result signal corresponding to the phase difference; and
a second delay control circuit, which receives said second phase comparison result signal and supplies said second delay control signal causing the phases of said reference clock and said second variable clock to coincide, respectively to the plurality of variable delay circuits constituting said second delay loop.
3. The DLL circuit, according to claims 1 or 2, wherein said .beta..degree. is over 180.degree..
4. The DLL circuit, according to claim 1, wherein said variable delay circuit comprises a plurality of logic gates connected in series, and the number of stages of said logic gates can be set variably by means of said delay control signal.
5. The DLL circuit, according to claim 1, further comprising an input buffer which receives an external clock and outputs said first clock; an output circuit which receives said control clock produced by said first variable delay circuit and generates a prescribed output at the timing of said control clock; and a dummy input buffer having a similar delay time to said input buffer and a dummy output circuit having a similar delay time to said output circuit both of which are provided in said first delay loop.
6. A semiconductor memory device which generates data output delayed by a prescribed phase .alpha..degree. from an external clock, a semiconductor memory device, comprising:
an output circuit, which receives a control clock and generates said data output;
an input buffer, which receives said external clock and output a first clock;
a first variable delay circuit which inputs said first clock and generates said control clock, in accordance with a first delay control signal; and
a DLL circuit which generates said first delay control signal;
wherein said DLL circuit comprises:
a first delay loop, which inputs said first clock and comprises a second variable delay circuit and a third variable delay circuit connected in series;
a first phase comparator, which compares a phase of a reference clock having a phase delay equal to an integral factor of 360.degree. from said first clock with a phase of a first variable clock output from said first delay loop, and generates a first phase comparison result signal corresponding to this phase difference;
a first delay control circuit, which receives said first phase comparison result signal and supplies said first delay control signal causing the phases of said reference clock and said first variable clock to coincide, to said second variable delay circuit and said first variable delay circuit; and
a .beta..degree. detecting circuit which generates a second delay control signal providing said third variable delay circuit with a delay time of .beta..degree. (=360.degree.-.alpha..degree.) from said first clock.
7. The semiconductor memory device, according to claim 6, wherein said .beta..degree. detecting circuit comprises:
a second delay loop, which inputs said first clock and comprises a plurality of variable delay circuits connected in series;
a second phase comparator, which compares the phase of said reference clock with the phase of a second variable clock output from said second variable loop, and generates a second phase comparison result signal corresponding to the phase difference; and
a second delay control circuit, which receives said second phase comparison result signal and supplies said second delay control signal causing the phases of said reference clock and said second variable clock to coincide, respectively to the plurality of variable delay circuits constituting said second delay loop.
8. The semiconductor memory device, according to claims 6 or 7, wherein said .beta..degree. is over 180.degree..
9. The semiconductor memory device, according to claims 6 or 7, wherein in said first delay loop, a dummy input buffer having a similar delay time to said input buffer and a dummy output circuit having a similar delay time to said output circuit.
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Description
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a DLL (Delayed Lock Loop) circuit which generates timing signals delayed by a prescribed phase with respect to an external reference clock, and a semiconductor memory device using same.
2. Description of the Related Art
In a synchronized semiconductor memory device, such as a synchronous DRAM (SDRAM) which performs high-speed operations in synchronism with a clock supplied by the system side, internal circuit operations are carried out in synchronism with the leading edge of the clock (phase: 0.degree.), for example, or at a timing delayed by a prescribed phase difference from the leading edge. In particular, in the case of an SDRAM, column type circuits are arranged in a pipeline configuration and pipeline gates provided between the plurality of pipeline circuits are opened by an internal control clock which is synchronized to the supplied clock, thereby causing the data in the memory cells to be transmitted and output.
However, recently, a DDR (double data rate) system has been proposed, which raises the data transfer rate by conducting internal pipeline operations in synchronism not only with the leading edge of the clock, but also with the trailing edge of the clock. In this DDR system, for example, the timing of internal operations is controlled by means of an internal control clock synchronized with the rise of the clock (phase difference 0.degree.), and an internal control clock synchronized with the fall of the clock (phase difference 180.degree.). Alternatively, the timing of internal operations may be controlled by means of an internal control clock which is delayed by 90.degree. from the rise of the clock, and an internal control clock which is delayed by 90.degree. from the fall of the clock (phase difference 270.degree. from the rise of the clock). In a further modification, the timing of internal operations may be controlled by means of an internal control clock which is phase delayed by A.degree. from the rise of the clock, and an internal control clock which is phase delayed by A.degree. from the fall of the clock.
In this case, it is necessary to generate internal control clocks delayed, respectively, by a phase of A.degree. and a phase of 180.degree.+A.degree. from the rise of the reference clock. A DLL circuit is known as a circuit for generating internal control clocks delayed by a prescribed phase from the rise of a reference clock. A DLL circuit comprises a phase comparing circuit which compares the phase of a first clock delayed by a prescribed phase from a reference clock with the phase of a second clock generated by a variable delay circuit to which this reference clock is supplied, and a delay control circuit which controls the amount of delay of the variable delay circuit in response to the phase difference detected by the phase comparing circuit, and it is able to generate an internal control clock delayed by a prescribed phase in the output of the variable delay circuit by controlling the delay control circuit such that there is a phase match between the rise of the first clock and the rise of the second clock.
A DLL circuit of this kind has been disclosed by the present applicant in Japanese Patent Application 8-339988 filled Dec. 19, 1996. |
