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Politics : Formerly About Advanced Micro Devices

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To: Elmer who wrote (70329)8/30/1999 6:45:00 PM
From: THE WATSONYOUTH  Read Replies (2) of 1573850
 
Re <The massive numbers of K6-3s flooding the market give us a hint as to AMD's inability to manufacture large caches & large die. The Athlon would need 512K on die L2 to make a difference and AMD has real problems manufacturing the K6-3 with 256K. The L2 doesn't care what the architecture is, it cares what the defect density is.>

Your point is well taken. However, remember this. If the K62/K63 designs originated from NexGen, they were designed for an IBM process that included a local interconnect level.
This local interconnect level allows a 12% - 15% advantage in SRAM cell size and a somewhat smaller advantage in logic density. However, it comes at a price. It is a difficult level from a processing point of view and, if not done correctly, a source of significant yield loss. My understanding is that AMD eliminated this level in the K7 design, opting for the more conventional easier approach. If so, this is probably a smart move on their part and may enable them to yield large L2 caches much more easily. Can anyone familiar with the history of K62/K63 confirm the local interconnect as being the main yield detractor and whether or not AMD did, in fact, abandon it in the K7 design? I asked this question in an earlier post and got ZERO response.

THE WATSONYOUTH
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