Formerly About Advanced Micro Devices Message Board

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next

To: Paul Engel who wrote (70702)	9/2/1999 3:47:00 AM
From: THE WATSONYOUTH	Read Replies (2) of 1574094

Re. <Motorola said the chip is being fabricated with a new 0.18-micron (0.15-micron L-effective) copper HiPerMOS process. All six levels of metal use copper instead of traditional aluminum interconnects. > Well, it sure does say that (.18um). But the numbers just don't add up for me. How could the G4 double in size over G3 (83mm2 vs. 40mm2) by adding AltiVec while at the SAME time going from .25um groundrules to .18um groundrules. That would mean the AltiVec addition would have to be much bigger than the entire original G3. I doubt it. Also, .15um Leff in .18um groundrules?? Intel is doing better than that in .25um groundrules. And, only 450MHz now in .18um? That's pathetic. Maybe they mean (.18um Ldrawn / .15um Leffective) for the gate level only and the groundrule generation is actually .25um. Then, at least, the numbers make some sense. If I'm wrong on this, I'll admit it on the thread but I am not ready to concede anything yet. THE WATSONYOUTH

Report TOU Violation

Share This Post

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next