Bilow,
Most non-technical people have no idea how fast 800MHz is. I'll try and explain. Each bit is only active for the length of time it takes light to travel about 15 inches.
Signals travelling along a printed circuit board trace slow to nearer half the speed of light, so each bit is actually about 8 inches long.
Rambus allows several such bits to be flying along the bus at any time, together with their associated clock edge. Other sdram technologies only allow one active bit on the bus at any one time. This means that there is some potential for future speeding up using, say, both clock edges at 133 MHz. However, those technologies will soon come up against the brick wall of needing to maintain only one bit on each bus line at any time, and this will translate into a maximum bus length for any particular speed. With Rambus, because there is a clock travelling with the data in either direction there is no such brick wall and it will be possible to increase the bus speed much, much more. The limitations then will be in overcoming transmission line imperfections at connectors and chip packages. One can envisage future Rambus sytems operating at clock speeds of many GHz, probably avoiding reflections from the stubs introduced by conventional bond wires by bringing the transmission lines onto and off the chip through constant impedance lead structures.
The problem with these really high speed interfaces is manufacturability. Some time when I feel like it, I may post some notes on worst case timing design. Until then, you are just going to have to take me at my word when I say that designing circuits that can sample data at 800MHz just isn't easy.
This is very true. However, it is much less difficult when there is a well designed transmission line structure with proper termination and drive circuits that do not themselves act as significant reflection sources. Without a constant-impedance transmission line, there is ringing caused by multiple reflections which uses up much of the extra time between bits.
Also the time aligned clock signal that travels alongside the data makes life much easier.
Motherboard designers are not likely to tune their boards up to the maximum speed that DDR can provide, which is why I am quoting 125MHz.
They may not like it, but speed increases whether from DDR 133 SDRAM or Rambus will require tighter manufacturing tolerances. It can be done - just look inside a cellular phone operating at 1.8 or 1.9 GHz which has impedance matched printed circuit structures including transmission lines, filters and directional couplers, all manufactured using mass-produced printed circuit technology. Or if you really want to see what can be done with printed circuit boards look inside a satellite television low-noise block.
My guess is that they will eventually get the bugs worked out, but I always thought this, and, in fact, at the beginning of this year I thought they would get the bugs worked out on schedule. They have not done this. This is a failure. There is no other way to describe it. Rambus failed to meet schedule, and it is in trouble, but not as much as INTC is, in my opinion.
I do agree with much of what you say, but I think the bugs are already worked out and that the very thorough design of the interface allowed this to be achieved much faster than many thought possible.
John |
