Hi John Walliker; Re those bits travelling on the rambus back plane &c.
DDR DRAM uses SSTL-2, not TTL switching levels. If you read the IEEE specification on it, you will find that it allows double terminations to the characteristic line impedance. In other words, there is no "brick wall" associated with DDR and multiple bits on a line. (I am having to suppress a cyber smile here, when I think about the concept of putting multiple bits on the same wire simultaneously. I think that if you do a little more research, you will find that nobody is making data lines on rambus long enough to suffer that particular feat. At 800Mhz, eight inches of copper is a long, long, long wire.)
You should also note that, identical to rambus, DDR sends a clock with the data. Rambus has no patent protection on this idea, it is ancient.
By the way, even with controlled impedance pins, putting more than two IC chips on the same wire is going to generate stubs. Engineers know this, and arrange for input signal rise and fall times to be slow enough to hide the stub reflections. This is why digital frequencies are so slow compared to what is theoretically possible. Amateur theoreticians just don't understand the actual limitations present in this technology. As an aside, you should ask around and find out more about how printed circuit boards are designed. In particular, the design time for controlled impedance boards is longer than that of regular boards, leading to delays in getting to market, as well as delays in fixing broken designs.
Regarding the well designed transmission line structure with proper termination and drive circuits that is supposed to give rambus an insurmountable advantage over DDR. After I have finished this post, I will go do a net search for the spec sheets on SSTL-2 and the DDR data bus. You can read it and find out that DDR also has a well designed transmission line structure. I will then either edit into this post, or if it takes more than 15 minutes, post it as a reply to this one. One of the amazing things about digital design right now, is the explosion in new logic definitions (i.e. LVTTL3, LVTTL2, CMOS2, CMOS3, SSTL-2, SSTL-3, HTL, etc.)
Tighter manufacturing tolerances increase the costs of the motherboard. What we are talking about here is controlled impedance inner layers, transmission line routing, etc. All this increases the cost of the motherboard on a per square inch basis. Thus rambus adds cost loading to more than just the rambus wires.
As far as the suggestions that digital engineers should be able to do it cause the communications guys do it at multi GHz, try to get real. Do you guys think that we are stupid? The next thing, people are going to start posting conspiracy theories on CPU design. The fact is that these things are designed by people who are very good, and who let no stone be unturned in their drive to out compete the competition. That is the way it has always been. It's a lot of fun, and only the very best get to play. So take a look at the circuitry inside your cellular phone. Notice that it isn't all on one chip? Ever wonder why? Do some research. If you can't tell me why it takes multiple chips to make a cellular phone with current technology, you have no business questioning my understanding of the limits of current technology, or suggesting that technology from some other field can be easily borrowed. Maybe I'll post some links on the difficulties associated with high frequencies and DRAM processes, not to mention LOGIC later on. (Hint, hint.)
-- Carl
P.S. Sorry for the chastisement in that last paragraph. I get a little hot under the collar some times, particularly when people imply that I could be doing my job better... |
