Bilow,
DDR DRAM uses SSTL-2, not TTL switching levels. If you read the IEEE specification on it, you will find that it allows double terminations to the characteristic line impedance. In other words, there is no "brick wall" associated with DDR and multiple bits on a line. (I am having to suppress a cyber smile here, when I think about the concept of putting multiple bits on the same wire simultaneously. I think that if you do a little more research, you will find that nobody is making data lines on rambus long enough to suffer that particular feat. At 800Mhz, eight inches of copper is a long, long, long wire.)
I have done my research. On the Rambus web site. There is a detailed description there of how multiple bits can be active on the same wire at the same time.
You should also note that, identical to rambus, DDR sends a clock with the data. Rambus has no patent protection on this idea, it is ancient.
Rambus has two clocks, one for each direction of data travel. DDR does not. Without this there cannot be multiple bits on the bus at once, as there would be no way of knowing which bit was being latched.
By the way, even with controlled impedance pins, putting more than two IC chips on the same wire is going to generate stubs. Engineers know this, and arrange for input signal rise and fall times to be slow enough to hide the stub reflections. This is why digital frequencies are so slow compared to what is theoretically possible.
Yes, that is why there are special packaging requirements for Rambus to minimise the stub.
Amateur theoreticians just don't understand the actual limitations present in this technology
Very true, but nor do they understand the great advantages that it will bring in the future.
As an aside, you should ask around and find out more about how printed circuit boards are designed. In particular, the design time for controlled impedance boards is longer than that of regular boards, leading to delays in getting to market, as well as delays in fixing broken designs.
Why? I have designed many printed circuit boards myself and have regular contact with manufacturers. High speed designs are much more likely to get broken if they are not designed using controlled impedance boards. After all, if the impedance is not specified, you don't know what you will get back from the manufacturers each time. As for the design time being longer, modern PCB design software has facilities for matching trace lengths and it is not difficult to determine the correct trace width to use in conjunction with a particular board lamination thickness and dielectric constant.
One of the amazing things about digital design right now, is the explosion in new logic definitions (i.e. LVTTL3, LVTTL2, CMOS2, CMOS3, SSTL-2, SSTL-3, HTL, etc.)
Yes, I have the i/o curves for most of those in front of me now. They all differ from the Rambus interface in one important aspect. Rambus drives the bus with constant current sources which do not cause a significant reflection when they are switched on.
Tighter manufacturing tolerances increase the costs of the motherboard. What we are talking about here is controlled impedance inner layers, transmission line routing, etc. All this increases the cost of the motherboard on a per square inch basis. Thus rambus adds cost loading to more than just the rambus wires.
Yes.
As far as the suggestions that digital engineers should be able to do it cause the communications guys do it at multi GHz, try to get real. Do you guys think that we are stupid?
Why not? How are computers going to get much faster than they are at present without using RF techniques much more. After all, it can be done and mass produced in the comms market.
So take a look at the circuitry inside your cellular phone. Notice that it isn't all on one chip? Ever wonder why? Do some research. If you can't tell me why it takes multiple chips to make a cellular phone with current technology, you have no business questioning my understanding of the limits of current technology, or suggesting that technology from some other field can be easily borrowed.
I have looked inside several cellular phones. Yes, I do know why there are several chips and why the number reduces every year. I am sure you do to. I also know that manufacturers are working towards integrating everything onto one chip, but they have not reached this point yet.
Maybe I'll post some links on the difficulties associated with high frequencies and DRAM processes, not to mention LOGIC later on. (Hint, hint.)
Please do - I am sure it will be of interest.
I get a little hot under the collar some times, particularly when people imply that I could be doing my job better...
I don't recall anyone suggesting that
John |
