AMD/INTC/RMBS et ALL Message Board

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : AMD/INTC/RMBS et ALL

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next

To: grok who wrote (6)	9/7/1999 2:39:00 PM
From: Dave B	Read Replies (1) of 271

KZ, Anyone understand the AL460GX Merced diagram that the Register posted. In the upper right it sez: "Dual Memory Ports; 4.2 GB/sec peak; 64 SDRAM DIMMS; 64 GB max." The chip set consists of a SAC address chip and a SDC data chip. Data from DIMMs moves at 266 MT/s so it must be 128 bits wide or else two 64b ports which must be what they mean by Dual Memory ports. Notice no Rambus anywhere. Old news. Check the Rambus thread (probably June/July timeframe, maybe earlier) for the discussion. The basic upshot of the discussion is that Merced was due out about a year before RDRAM was due out, so RDRAM was obviously not included in the design. As Merced slipped, the last thing they would have done would have been to change the memory interface to another new technology. They're trying to get it done, not continue to upgrade it (no creeping elegance!). Search for Merced and Rambus on the regular thread. You'll probably be able to find it. Dave

Report TOU Violation

Share This Post

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next