SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Rambus (RMBS) - Eagle or Penguin
RMBS 88.13+1.0%Nov 21 9:30 AM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Bilow who wrote (28889)9/8/1999 9:25:00 AM
From: John Walliker  Read Replies (2) of 93625
 
Carl,

Hi John Walliker; DDR does use a different clock for different directions of data travel. Take a look at the pinout. The x16 part has a total of 4 clock lines.
-- Carl
P.S. The byte-wide data clocks are bidirectional, with direction depending on the data direction.


I downloaded the datasheet you posted a link to. It is only advance data and has no detailed timing info.

The reason the x16 part has more clock lines is that it uses differential clocking, most likely because of ground bounce problems with the larger number of data lines. (Rambus also uses differential clocking.)

The data sheet confirms my assertion that it does not use two clocks travelling in opposite directions on separate clock lines. Instead it uses a bidirectional data strobe as you pointed out, in addition to a master clock. This means that the controller has to generate a master clock and a data strobe signal, with appropriate relative timing when it is writing to the chip, along with chip select and write enable signals. Then when data is read from the chip the chip itself generates its own data strobe signal on the same wire as the write data strobe that clocks the data back into the controller.

Are you trying to say that this is simpler and easier to implement than one clock that loops past all the chips in one direction, past the controller and then back to the termination like Rambus?

The DDR interface is much more complex and will have a much higher power consumption. There are many different control signals which must all be timed correctly. This will become a nightmare when further speed increases are attempted. Rambus will scale up to much higher speeds.

The DDR data confirms that this technology does not support multiple bits active on the bus at one time, in contrast to Rambus which already does according to published data.

Therefore DDR will hit a performance brick wall which does not exist for Rambus.

John
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext