Carl,
Some more thoughts about your post.
Rather than comparing systems with three DDR RAMS in parallel lets
get realistic and use four 16-bit DDR RAMS of the type you suggested from IBM
(IBM0625164).
A minimum system using these devices would have a total capacity of 128 Mbyte
and a data transfer rate of 1.6 Gbyte/s at 100 MHz or 2.1 Gbyte/s at 133 MHz.
There is no immediate prospect of 143 MHz chipset support, so lets forget about
the 7ns cycle time you used.
Comparisons are easier if the same peak data transfer rate is used, so lets work
at 100MHz.
We are assuming a hard-working system, so all four banks of the IBM device
would be active. For burst accesses the supply current will be about 100mA.
This number comes from the -12 part, where the minimum cycle time is 8ns.
Therefore, the total RAM supply current (not including bus drive) will be
about 400mA @2.5V
To achieve the same memory capacity with DRDRAM will require eight chips,
of which one will typically be active and the others in standby or sleep mode.
The active chip will take 490mA max read current or 575mA max write current.
Say 507 mA average for a 4:1 read/write ratio.
If all the other chips are in NAP mode, drawing 4mA each then the total current
(excluding bus drive) will be 507 + 7*4 = 535mA.
If all the other chips are in STBY mode, then the total current will be (excluding
bus drive) will be 507 + 7*105 = 1242mA. This is a worst case figure. The real
power consumption will probably be somewhere in between, so lets assume half
the chips are in NAP mode, the rest in STBY or ATTN (active).
Then the Rambus supply current (excluding bus drive) will be
507 + 4*4 + 3*105 = 838 mA.
OK. This is just over twice as much as the IBM 256 Mbit chips, but not the
factor of 3.7 or 6.6 you claim.
Your assumption is that the factor of 6.6 applies to portable systems where as many
of the chips are inactive as possible, but according to my analysis the relevant
ratio would be 535/400 = 1.34.
Also remember that we are comparing IBM 256Mbit DDR chips with Samsung 128Mbit chips.
Samsung have announced that they will be shipping 256 Mbit devices within the next
few months. These will undoubtedly push the equation more in favour of Rambus.
Now lets look at the power consumption of the bus.
The IBM DDR chips use SSTL2 signalling where the static drive current from each pin is
about 15mA.
There are 42 signal pins per chip, but many of them only need to be driven once per
four chips. Only the data lines will be independent. Therefore 16*4 + 42-16 = 90
individual pins are likely to be driven at once. Therefore 90*15=1350mA system supply
current is needed to drive the bus. This value will be significantly higher under
dynamic conditions.
For Rambus, there are 28 pins carrying Rambus signalling level. All the others are CMOS
and can be ignored. The drive current on each pin is about 30 mA for logic 1
and zero for logic 0. Therefore average current is about the same as for SSTL2 at 15mA
per pin.
Therefore, total average current used for Rambus signalling is about 15*28=420mA.
Adding chip and bus supply currents up gives the following:
DDR using four IBM 256k bit chips 400 + 1350 = 1750 mA
Rambus using eight Samsung 128k bit chips 838 + 420 = 1258 mA (half of chips in NAP mode).
Therefore, the system power consumption using Rambus is about 1.4 times LOWER than DDR
even though the Rambus chips used in this example are of an older generation than the
DDR ones.
John
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