Hi Alan Bell; Re: "For a signal with a rise time of 2ns, the maximum acceptable length would be 2.3 inches. So a system could be left unterminated if the data signals are less than 2.3 inches."
I don't have the spec in front of me, but my guess is that the rise time would be somewhat less than 2ns, so rule of thumb length would be less. But instead of using a thumb rule, modern practice is to simulate.
In the case of the hypothetical DDR system we have been talking about, most of the wires are data bus wires. So it is these we should consider first.
Since it is a data bus, the primary concern is that setup and hold be met on the receiving flip flop. It is possible for a bus that rings pretty long to still meet setup and hold times.
The address lines are running at a lower frequency, and are only sampled at one edge per 10ns. So while they have more pins, and thus worse ringing, they also have more time available for the ringing to die out.
The effect of the ringing is to reduce the "data eye." But since we are using 8ns parts with a 10ns period, we already have a nanosecond of extra eye time on the data bus, and a full 2ns of time on the control bus. In addition, as you will find in the SSTL_2 specification, this logic family is specifically designed to be immune to a certain amount of ringing.
My coworker who knows the most about these sorts of things says that it will work with no termination, but in reality, the engineer would have to run simulations if more than one RDRAM chip were placed on the data bus. (The hypothetical example we were discussing only had one bank of DDR.)
On the other hand, there is no doubt that the clock lines need to be correctly terminated, though, and I felt guilty all day yesterday for not mentioning this in my post. What can I say? It was very late, and I have been very busy. I expected to be inundated with posts saying that I was an idiot, you guys are really too kind to me.
You go on to say: "But if they are longer than this, termination is required." As noted above, this statement is necessarily true only for the clocks. In fact, common practice is to terminate all clocks regardless of the length. This is to avoid double clocking and uncontrolled skew.
But the next sentence: "This will then use the kind of power that John describes", is not correct. This assumes that the only termination is the parallel type, which is not the case.
Here are some quotes from and a link to an applicable Triquint (TQNT) application note (they make high speed clock driver chips):
Terminating Clock Lines
page 3
Series Termination
Series termination, as shown in Figure 4, is the most common termination scheme used in clock distribution schemes. It consumes less power than other termination techniques and requires only a single resistor. The second example illustrates the use of series termination to minimize reflections.
page 5.
Advantages and Disadvantages of Series Termination
Because series termination does not require additional power, it is a good choice when power dissipation is a critical design concern. When driving CMOS inputs, the steady-state power at the output is near zero,
triquint.com
Your choice of parallel termination for the DDR designs is a poor choice, and one that good memory designers are unlikely to make, though I would be inclined to include parallel termination on the one master clock, at least on the prototypes, and would probably include DNIs on the other control lines.
By the way, if the data bus does give termination problems, (not in the design we are discussing, but in some larger design), these are traditionally alleviated with series resistors.
In other words, my calculations for DDR power consumption are quite correct.
Rambus is a power hog, there is no way around this fact.
-- Carl |
