dan - Re; Chevyman
<Since both FAb25 and Fab30 are identical as far as the production floor is involved then all AMD has to do is follow is previous plans for installing tools. The difference this time is that they don't have to develop the process as we did in Fab25. Most of the delays in the k5 and k6 were strickly tool problems. I know, one problem tool that cost AMD months and months of delays was my tool set. It was an experimental tool and was rushed to the fab too early. It cost AMD 4-5 months delay itself. In fab25 everything was new, the process, workers,tools, engineers,etc. It's different this time they know the tools abilities now, they know the process and design now and they are not having to deal with experimental tool sets on production runs like we did in Fab25 for the first 2 years.>
Sounds like a normal fab guy in the throes of a ramp. It can get frustrating when tool(s) experience problems when bringing them up. That's where Intel's manufacturing redundancy is a BIG BIG asset. I cannot stress this enough. I feel for the guy / situation. This is one big reason that comparatively AMD has inherently more risk in it's model, not that they can really do anything about it other than what they are doing now, except...
<The real problem with copper is contamination not is placement or usage. Copper is so soft as to become a problem with everything it touches causing a transfer that leads to contamination in tools and transfer equipment. Copper could be used in anything that needs a circuit or contact but, you have to weigh the cost vs results. If the copper does not enhance the chip enough why use it considering the extra trouble to keep the contamination issues out. There is enough money in a high end CPU chip to make the cost vs rewards significant enough for the effort required.>
You all know my mantra here. I believe Dresden and Austin should have been brought up on Al at .18. This would have given them some redundancy to their operation. I also don't believe that Cu is worth the small performance gain on .18, as the trade off as I see it is process variation and stability. But you all knew I'd say that :-).
<I am not sure we will ever reach .13 with the current litho technology. We are probably going to have to change to xray litho tech to get that low. I have however seen post in tech mags that say it is possible with current tech. used at U of T. the problem at .13 is in the contacts that connect the layers of circuits etched on a chip. At .13 you run into the problem that the contacts are so narrow that getting the contact material (whatever it is) to flow down and fill the contact without a void is nearly impossible. The reason I say that is because of the size of the atoms of current materials used make it a real problem to fill the voids. The voisd of course causse a yield problem. That is one of the many reasons for the change to copper at this time. It folws better that th Au tha tis currently being used and the Au currently being used will not fill those gaps without a problem. Someone earlier posted .09mu possibilities, I say not witha todays tools and technology. Hell look at he great Intel..It's having considerable problems with .18mu. Look for new materials to be used in the future and look for taller chips. The k5 was a 5 layer metal chip..k6 a 6 layer metal chip..k7 now has 7 layers of circuits etched on it. What will the k8 be????>
Lithography capability is and always has been pushed to its limits, and is a process constraint. It's always been that way and probably always will. Someone at AMD is working feverishly on patterning and developing .13 linewidth capability, or at least someone should be. I can't comment specifically on Intel's .13 litho strategy.
<You say it will take a few years to reach 5000WSW. Well amd did 5000WSW in Fab25 in its first year and a half. Dresden has been funning a year and they were already familiar with the tools since they are the same as the ones in Fab25. That should have taken some of the lead time out of the mix. I will concede some time to the shrink for .18 however and agree that full capacity probably not for a few more months.>
If it takes YEARS to get to 5000 wafers per week, something is really wrong. Dresden should get there next year if all goes well.
<Just thoughthat I would remind you that the tools in Fab 30 have been there and qualling for a year now. Do you think in a year that they could figure the tools out and get them up and running?
Yep they can!! Dresden is up and running production and not a measly 800WSW. Hell 800 wafers a week leaves the tools idle and the employees asleep since most tools have multiple chambers allowing them to run an average of 62 wafers per tool per runcycle. >
This place IS ramping slow for some reason. I can only speculate as to why. I would guess the process just isn't ready, yet, as this guy is saying they are running wafers >800 per week for a year(?)(probably experiments and baseline SRAM). It may be ready tomorrow for all I know though.
Overall, I believe this person to be a real AMD fab employee, probably on the manufacturing side. If he continues to post, one may be able to glean some indication of what's going on at F25. This person obviously is getting cursory updates on Dresden, but probably does not have direct visibility.
Still interesting though.
PB |
