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Politics : Formerly About Advanced Micro Devices

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To: Process Boy who wrote (72321)	9/19/1999 5:15:00 PM
From: Dan3	Read Replies (2) of 1572579

by: Chevyman1963 65127 of 65130 Fact.. Before Liu was introduced to contact 2 layers of circuits you did what is called "contact etch" which basically meant you put a barrrier over the first "circuit" layer and etched contact "holes" that were filler with tungsten to contact up to the next"layer of circuit. With 3 layer metal theis was pretty simple and not very involved. With the advent of the 5 layer and later 6 layer metal circuits problems started to surface. Esentially to keep chips small we went up instead of out and in so doing added circuits on top of one another. The problem is that sometimes the bottom layer needs to be connected to the top or upper layers and therefore the li etch has to extend down 3/4 or even 5 layers and must not be covered up by the circuits above it. The li etch is not a direct etch like the contacts were eg: a straight hole straight down. The li etch is an etch that shoots for a specific area the the underlying circuit should be at. Then you lay the next layer onto the chip and the holes are filled. One of the problems that I alluded to in another post was that sometimes the lower contact area gets etched or eaten away before it is filled at the later metal layer laying. That is what happened to the inital runs of k6. When the resist was removed the contact area for the li etch was eaten away by the chemicals that removed the resist. This was not suppose to be possible and took AMD months to track down. The reason it took so long to track down was that all the li etch areas were covered by no contact was made because the lower area was already gone. Remember todays etch is a dry etch and is very very harsh because of the chemicals used along with the plasma etch process. Once the problem was identifies by partitioniong off the processes yields jumped from 3% to 75% within days. OIbviously I am not detailing everything that is done just giving you the gist of what is done. Remember it takes ~255 processes and ~50 days to complete a wafer. Obviously I have tried to simplify and there is a lot more involved. This is all information and those of you that want to believe it can and those that don't .. Go back to the Intel board. I recommend no investments and just share info to those that ask..If I know I may answer ..if I don't I'll tell ya. Did ya see those Cowboys??? Gooo Chevy Gooo AMD

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