Re: "Elmer, the full speed cache(which may limit it to 650-700max) might allow the .18 P-III to close the gap to same speed Athlons, but it will not beat them as it still lacks the architecture to beat the Athlons. The exception might be SSI written stuff....of which there is not much, esp in business. The Athlon is still early in it's development cycle and there are a number of derivatives to follow, such as full speed caches of varying sizes, copper based fabbery as well as .18 die shrinx. Is fabbery a new word or how a new york taxidriver says the second month<GGG> Gateway was aided in the decision by the breeze from 20 million dollars waving hard.....blew AMD right out the door."
Architecture enhancements look great on paper but how do the stack up against simple on-die cache? We will soon see. Full speed cache off-die is not the same as on-die and AMD has demonstrated a real problem manufacturing large on-die L2 devices, witness the K63. The Athlon would have to be at least twice the L2 size of the K63 to be of any use and it's already huge without it.
In contrast, Intel has shown they can manufacture huge die. They are manufacturing a 1.5Meg L1 HP die, as well as their 128K Celeron and 256K L2 Dixon. Coppermine will soon be available at 256K L2 and up. 6 Fabs running flat out. Oregon, New Mexico, Arizona, Ireland, Israel and Santa Clara.
Copper is way overblown and AMD is already down to .18u channel lengths, so don't hope for a big MHz bump, just a die size shrink when going to .18u full design rules.
In the final analysis, can AMD make any money or will they simply have run out of things to pawn off?
EP |
