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Politics : Formerly About Advanced Micro Devices
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To: tejek who wrote (72681)9/21/1999 2:59:00 PM
From: Shane Geary  Read Replies (1) of 1575420
 
Ted: Re: "TSMC is estimating a 10% loss of wafers."

I can't see where is says that in the article, but then I'm a bit tired.

As PB has stated, there shouldn't be a huge loss in wafers.

Take a typical fab, with 20% of wafers in the diffusion/LPCVD/thermal oxide areas - ie anything that uses a furnace. About half of these will be running, if you're unlucky. So max loss is about 10%. However, if these are non-critical furnace cycles there is a good chance that they could be recovered (if you have well-characterised cycles). Thus maybe the loss would be only 5%.

Other batch processes include ion implantation (eg 12 wafers at a time). Again, the furnaces should be able to record how much implant had taken place when power stopped and non-critical implants should be able to be recovered.

Wet benches used for wet etches and oxide/nitride strips may have >100 wafers running per bench and could lose all wafers.

All etchers, most CVD tools (except furnace LPCVD) and resist strippers should be OK. Lithography will be fine.

So, I'd be surprised that 10% of wafers get lost. Typical power cuts/glitches here usually cost <1% of wafers.

How much more than a simple power cut was involved is the question, I guess.

Shane
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