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To: Rob Young who wrote (88672)	9/22/1999 4:56:00 PM
From: Tenchusatsu	Read Replies (2) of 186894

Rob, no need to get all riled up. Here's the quote from MPR regarding the Alpha 21364's L2 cache: One potential problem is the L2 access time. Whereas the 21164 was thought to be deficient with a six-cycle access, the 21364 requires twice that. Even Intel's Mendocino, not exactly a paragon of performance, needs only eight cycles to access its on-chip L2 cache. Its impressive 80-entry reorder buffer notwithstanding, the 21364 is unlikely to queue enough instructions to avoid stalling during a 12-cycle L1 cache miss. I never said anything about performance-per-clock, and even MPR's article had to put in that little disclaimer regarding the comparison. All I said is that the L2 latency of Mendocino is 8 clocks, and I tossed up some theories as to why it isn't shorter by drawing some analogies to the Alpha 21364. Obviously, I would never be able to say that Mendocino Celeron can outperform an Alpha 21364 and keep a straight face. (Steve Jobs could if he worked for Intel, but that's a different story.) Tenchusatsu

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