Carl,
Hi John Walliker; I'm sorry, but I just can't let this one go by without correction. The reason is because metastability is a subject near and dear to me.
I may not be quite so intimately involved with metastability as you, but have left devices connected to a digital storage 'scope on infinite persistence for days at a time with marginal timing to explore metastability properties of particular devices when I was trying to locate some of those elusive once-in-a-blue-moon faults. So I do know what it is and have a feel for it.
The fact is that the specification provides a time region where the part is guaranteed to operate under. Any particular device is sure to operate under an even wider range of times. Getting metastability isn't particularly easy, just busting the setup or hold will not get it very often. Instead of having to do with the amount that a specification is abused, the metastability exponential decay parameters have to do (1) predicting the actual width of the metastability zone, and (2) predicting the duration of metastability, once that state is entered.
That guarantee simply means that the device will not fail for a time deemed by the manufacturers to be long enough. The duration of metastability does depend on the extent to which the setup time is violated. Whether or not it matters depends on how long after the clock edge the next stage of logic needs its input to be stable.
These are all manifestations of the same underlying phenomenon.
No big surprise here, your results are counter-intuitive.
But I then went on to say that DDR RAM does not use a constant impedance transmission line and therefore a significant part of that time is wasted in waiting for the bus to settle.
Re: "Because of the exponential metastability relationship which will be much steeper for the faster DRDRAM data latches, less extra time is needed to provide an equivalent safety margin." This statement has no connection to engineering. The safety margin was calculated above, it is not the time that the data must be valid, it is, instead, the time that is available to switch the data. And incidentally, the exponential metastability characteristics depend on the design details of the flip-flops used in the two systems, and, given that they are running on the same process, and therefore can implement identical flip-flops, the metastability numbers are likely to be identical.
What I was trying to say was that if a particular setup time gives a probability of error of say once per year, then adding a few extra picoseconds will reduce the error probability more for the faster device than the slower.
And incidentally, the exponential metastability characteristics depend on the design details of the flip-flops used in the two systems, and, given that they are running on the same process, and therefore can implement identical flip-flops, the metastability numbers are likely to be identical.
Explain why the specified setup and hold time window is longer for the IBM 256Mbit DDR process than the older and slower Samsung 128Mbit DRDRAM process.
Could it be due to design differences in the data latches that form part of the Rambus interface?
But metastability has nothing to do with working memory systems. When a memory designer starts computing metastability numbers (for the data paths), it is a sign that something has gone seriously wrong. None of the metastability calculations has much to do with the inherent safety of DRDRAM.
But it was you who introduced the subject of metastability. I totally agree with your earlier statement that it is very important. It provides insight into why systems can fail randomly and how to avoid this. It explains why overclocked systems will often work for a considerable length of time before failing for no obvious reason.
John |
